Only in ral-current-netbsd-current/src/share/man/man4: ral.cat4 diff -ru ral-netbsd-1.0/src/sys/dev/ic/ral.c ral-current-netbsd-current/src/sys/dev/ic/ral.c --- ral-netbsd-1.0/src/sys/dev/ic/ral.c 2005-03-12 12:44:41.000000000 +0100 +++ ral-current-netbsd-current/src/sys/dev/ic/ral.c 2005-05-03 15:40:46.000000000 +0200 @@ -70,8 +70,8 @@ /*#define RAL_DEBUG*/ #ifdef RAL_DEBUG -#define DPRINTF(x) if (ral_debug > 0) printf x -#define DPRINTFN(n, x) if (ral_debug >= (n)) printf x +#define DPRINTF(x) do { if (ral_debug > 0) printf x; } while (0) +#define DPRINTFN(n, x) do { if (ral_debug >= (n)) printf x; } while (0) int ral_debug = 3; #else #define DPRINTF(x) @@ -142,6 +142,8 @@ static void ral_set_macaddr(struct ral_softc *, uint8_t *); static void ral_get_macaddr(struct ral_softc *, uint8_t *); static void ral_update_promisc(struct ral_softc *); +static void ral_set_txantenna(struct ral_softc *, int); +static void ral_set_rxantenna(struct ral_softc *, int); static const char *ral_get_rf(int); static void ral_read_eeprom(struct ral_softc *); static int ral_bbp_init(struct ral_softc *); @@ -176,8 +178,8 @@ { RAL_CSR11, 0x07041483 }, { RAL_CNT3, 0x00000000 }, { RAL_TXCSR1, 0x07614562 }, - { RAL_TXCSR8, 0x8c8d8b8a }, - { RAL_ARTCSR0, 0x7038140a }, + { RAL_ARSP_PLCP_0, 0x8c8d8b8a }, + { RAL_ACKPCTCSR, 0x7038140a }, { RAL_ARTCSR1, 0x1d21252d }, { RAL_ARTCSR2, 0x1919191d }, { RAL_RXCSR0, 0xffffffff }, @@ -189,7 +191,7 @@ { RAL_PWRCSR1, 0x000001ff }, { RAL_MACCSR0, 0x00213223 }, { RAL_MACCSR1, 0x00235518 }, - { RAL_MACCSR2, 0x00000040 }, + { RAL_RLPWCSR, 0x00000040 }, { RAL_RALINKCSR, 0x9a009a11 }, { RAL_CSR7, 0xffffffff }, { RAL_BBPCSR1, 0x82188200 }, @@ -216,8 +218,8 @@ { 21, 0x08 }, { 22, 0x08 }, { 23, 0x08 }, - { 24, 0x70 }, - { 25, 0x40 }, + { 24, 0x80 }, + { 25, 0x50 }, { 26, 0x08 }, { 27, 0x23 }, { 30, 0x10 }, @@ -271,6 +273,16 @@ 0x20464, 0x20465, 0x20466, 0x20467, 0x20468, 0x20469, 0x2046b }; +static const uint32_t ral_rf2526_hi_r2[] = { + 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d, 0x0022d, + 0x0022e, 0x0022e, 0x0022f, 0x0022d, 0x00240, 0x00240, 0x00241 +}; + +static const uint32_t ral_rf2526_r2[] = { + 0x00226, 0x00227, 0x00227, 0x00228, 0x00228, 0x00229, 0x00229, + 0x0022a, 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d +}; + /* * For dual-band RF, RF registers R1 and R4 also depend on channel number; * values taken from the reference driver. @@ -325,6 +337,11 @@ { 161, 0x08808, 0x0242f, 0x00281 } }; +#ifdef __NetBSD__ +#define letoh32 htole32 +#define letoh16 htole16 +#endif + int ral_attach(struct ral_softc *sc) { @@ -419,7 +436,7 @@ ic->ic_sup_rates[IEEE80211_MODE_11G] = ral_rateset_11g; /* set supported .11b and .11g channels (1 through 14) */ - for (i = 1; i <= 11; i++) { + for (i = 1; i <= 14; i++) { ic->ic_channels[i].ic_freq = ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); ic->ic_channels[i].ic_flags = @@ -484,8 +501,8 @@ if_detach(ifp); ral_free_tx_ring(sc, &sc->txq); - ral_free_tx_ring(sc, &sc->prioq); ral_free_tx_ring(sc, &sc->atimq); + ral_free_tx_ring(sc, &sc->prioq); ral_free_tx_ring(sc, &sc->bcnq); ral_free_rx_ring(sc, &sc->rxq); @@ -717,7 +734,6 @@ MCLGET(data->m, M_DONTWAIT); if (!(data->m->m_flags & M_EXT)) { - m_freem(data->m); aprint_error("%s: could not allocate rx mbuf cluster\n", sc->sc_dev.dv_xname); error = ENOMEM; @@ -902,9 +918,12 @@ break; case IEEE80211_S_ASSOC: + ral_set_chan(sc, ic->ic_bss->ni_chan); break; case IEEE80211_S_RUN: + ral_set_chan(sc, ic->ic_bss->ni_chan); + if (ic->ic_opmode != IEEE80211_M_MONITOR) { ral_set_bssid(sc, ic->ic_bss->ni_bssid); ral_update_slot(sc); @@ -969,7 +988,7 @@ RAL_EEPROM_CTL(sc, RAL_EEPROM_S | RAL_EEPROM_C); /* Write address (A5-A0 or A7-A0) */ - n = (RAL_READ(sc, RAL_CSR21) & RAL_CSR21_93C46) ? 5 : 7; + n = (RAL_READ(sc, RAL_CSR21) & RAL_EEPROM_93C46) ? 5 : 7; for (; n >= 0; n--) { RAL_EEPROM_CTL(sc, RAL_EEPROM_S | (((addr >> n) & 1) << RAL_EEPROM_SHIFT_D)); @@ -1042,7 +1061,7 @@ } /* kick Tx */ - RAL_WRITE(sc, RAL_TXCSR0, RAL_TXCSR0_KICK_TX); + RAL_WRITE(sc, RAL_TXCSR0, RAL_KICK_TX); } static void @@ -1076,11 +1095,13 @@ ieee80211_rssadapt_raise_rate(ic, &rn->rssadapt, &data->id); } + ifp->if_opackets++; break; case RAL_TX_SUCCESS_RETRY: DPRINTFN(9, ("data frame sent after %u retries\n", (le32toh(desc->flags) >> 5) & 0x7)); + ifp->if_opackets++; break; case RAL_TX_FAIL_RETRY: @@ -1090,6 +1111,7 @@ ieee80211_rssadapt_lower_rate(ic, data->ni, &rn->rssadapt, &data->id); } + ifp->if_oerrors++; break; case RAL_TX_FAIL_INVALID: @@ -1225,12 +1247,16 @@ (le32toh(desc->flags) & RAL_RX_CIPHER_BUSY)) break; - if (data->drop) + if (data->drop) { + ifp->if_ierrors++; goto skip; + } if ((le32toh(desc->flags) & RAL_RX_CIPHER_MASK) != 0 && - (le32toh(desc->flags) & RAL_RX_ICV_ERROR)) + (letoh32(desc->flags) & RAL_RX_ICV_ERROR)) { + ifp->if_ierrors++; goto skip; + } bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); @@ -1370,7 +1396,7 @@ } /* kick decrypt */ - RAL_WRITE(sc, RAL_SECCSR0, RAL_SECCSR0_KICK); + RAL_WRITE(sc, RAL_SECCSR0, RAL_KICK_DECRYPT); } /* @@ -1383,7 +1409,8 @@ struct ieee80211com *ic = &sc->sc_ic; struct ral_tx_data *data; - if (ic->ic_opmode != IEEE80211_M_IBSS) + if (ic->ic_opmode != IEEE80211_M_IBSS && + ic->ic_opmode != IEEE80211_M_HOSTAP) return; data = &sc->bcnq.data[sc->bcnq.next]; @@ -1427,29 +1454,29 @@ r = RAL_READ(sc, RAL_CSR7); RAL_WRITE(sc, RAL_CSR7, r); - if (r & RAL_CSR7_BEACON_EXPIRE) + if (r & RAL_BEACON_EXPIRE) ral_beacon_expire(sc); - if (r & RAL_CSR7_WAKEUP_EXPIRE) + if (r & RAL_WAKEUP_EXPIRE) ral_wakeup_expire(sc); - if (r & RAL_CSR7_ENCRYPTION_DONE) + if (r & RAL_ENCRYPTION_DONE) ral_encryption_intr(sc); - if (r & RAL_CSR7_TX_DONE) + if (r & RAL_TX_DONE) ral_tx_intr(sc); - if (r & RAL_CSR7_PRIO_DONE) + if (r & RAL_PRIO_DONE) ral_prio_intr(sc); - if (r & RAL_CSR7_DECRYPTION_DONE) + if (r & RAL_DECRYPTION_DONE) ral_decryption_intr(sc); - if (r & RAL_CSR7_RX_DONE) + if (r & RAL_RX_DONE) ral_rx_intr(sc); /* re-enable interrupts */ - RAL_WRITE(sc, RAL_CSR8, RAL_CSR8_MASK); + RAL_WRITE(sc, RAL_CSR8, RAL_INTR_MASK); return 1; } @@ -1577,10 +1604,7 @@ desc->flags |= htole32(RAL_TX_OFDM); desc->physaddr = htole32(physaddr); - desc->wme = htole32( - 8 << RAL_WME_CWMAX_BITS_SHIFT | - 3 << RAL_WME_CWMIN_BITS_SHIFT | - 2 << RAL_WME_AIFSN_BITS_SHIFT); + desc->wme = htole16(RAL_LOGCWMAX(8) | RAL_LOGCWMIN(3) | RAL_AIFSN(2)); /* * Fill PLCP fields. @@ -1740,9 +1764,8 @@ data->m = m0; data->ni = ni; - ral_setup_tx_desc(sc, desc, RAL_TX_IFS_NEW_BACKOFF | - RAL_TX_INSERT_TIMESTAMP, m0->m_pkthdr.len, rate, 0, - data->map->dm_segs->ds_addr); + ral_setup_tx_desc(sc, desc, RAL_TX_IFS_NEWBACKOFF | RAL_TX_TIMESTAMP, + m0->m_pkthdr.len, rate, 0, data->map->dm_segs->ds_addr); bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, BUS_DMASYNC_PREWRITE); @@ -1798,7 +1821,7 @@ wh = mtod(m0, struct ieee80211_frame *); if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { - flags |= RAL_TX_NEED_ACK; + flags |= RAL_TX_ACK; dur = ral_txtime(RAL_ACK_SIZE, rate, ic->ic_flags) + RAL_SIFS; *(uint16_t *)wh->i_dur = htole16(dur); @@ -1808,7 +1831,7 @@ IEEE80211_FC0_TYPE_MGT && (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == IEEE80211_FC0_SUBTYPE_PROBE_RESP) - flags |= RAL_TX_INSERT_TIMESTAMP; + flags |= RAL_TX_TIMESTAMP; } ral_setup_tx_desc(sc, desc, flags, m0->m_pkthdr.len, rate, 0, @@ -1826,7 +1849,7 @@ /* kick prio */ sc->prioq.queued++; sc->prioq.cur = (sc->prioq.cur + 1) % RAL_PRIO_RING_COUNT; - RAL_WRITE(sc, RAL_TXCSR0, RAL_TXCSR0_KICK_PRIO); + RAL_WRITE(sc, RAL_TXCSR0, RAL_KICK_PRIO); return 0; } @@ -1870,6 +1893,7 @@ struct ral_tx_desc *desc; struct ral_tx_data *data; struct ral_node *rn; + struct ieee80211_rateset *rs; struct ieee80211_frame *wh; struct mbuf *mnew; uint16_t dur; @@ -1878,10 +1902,17 @@ wh = mtod(m0, struct ieee80211_frame *); - rn = (struct ral_node *)ni; - ni->ni_txrate = ieee80211_rssadapt_choose(&rn->rssadapt, &ni->ni_rates, - wh, m0->m_pkthdr.len, ic->ic_fixed_rate, sc->sc_dev.dv_xname, 0); - rate = ni->ni_rates.rs_rates[ni->ni_txrate] & IEEE80211_RATE_VAL; + if (ic->ic_fixed_rate != -1) { + rs = &ic->ic_sup_rates[ic->ic_curmode]; + rate = rs->rs_rates[ic->ic_fixed_rate]; + } else { + rs = &ni->ni_rates; + rn = (struct ral_node *)ni; + ni->ni_txrate = ieee80211_rssadapt_choose(&rn->rssadapt, rs, + wh, m0->m_pkthdr.len, -1, NULL, 0); + rate = rs->rs_rates[ni->ni_txrate]; + } + rate &= IEEE80211_RATE_VAL; if (ic->ic_flags & IEEE80211_F_PRIVACY) { m0 = ieee80211_wep_crypt(ifp, m0, 1); @@ -1932,7 +1963,7 @@ /* RTS frames are not taken into account for rssadapt */ data->id.id_node = NULL; - ral_setup_tx_desc(sc, desc, RAL_TX_NEED_ACK | RAL_TX_NOT_LAST, + ral_setup_tx_desc(sc, desc, RAL_TX_ACK | RAL_TX_MORE_FRAG, m->m_pkthdr.len, rtsrate, 1, data->map->dm_segs->ds_addr); bus_dmamap_sync(sc->sc_dmat, data->map, 0, @@ -2014,13 +2045,16 @@ data->ni = ni; /* remember link conditions for rate adaptation algorithm */ - data->id.id_len = m0->m_pkthdr.len; - data->id.id_rateidx = ni->ni_txrate; - data->id.id_node = ni; - data->id.id_rssi = ni->ni_rssi; + if (ic->ic_fixed_rate == -1) { + data->id.id_len = m0->m_pkthdr.len; + data->id.id_rateidx = ni->ni_txrate; + data->id.id_node = ni; + data->id.id_rssi = ni->ni_rssi; + } else + data->id.id_node = NULL; if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { - flags |= RAL_TX_NEED_ACK; + flags |= RAL_TX_ACK; dur = ral_txtime(RAL_ACK_SIZE, ral_ack_rate(rate), ic->ic_flags) + RAL_SIFS; @@ -2042,7 +2076,7 @@ /* kick encrypt */ sc->txq.queued++; sc->txq.cur_encrypt = (sc->txq.cur_encrypt + 1) % RAL_TX_RING_COUNT; - RAL_WRITE(sc, RAL_SECCSR1, RAL_SECCSR1_KICK); + RAL_WRITE(sc, RAL_SECCSR1, RAL_KICK_ENCRYPT); return 0; } @@ -2120,6 +2154,7 @@ aprint_error("%s: device timeout\n", sc->sc_dev.dv_xname); ral_init(ifp); + ifp->if_oerrors++; return; } ifp->if_timer = 1; @@ -2308,6 +2343,15 @@ ral_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00286 : 0x00282); break; + case RAL_RF_2526: + ral_rf_write(sc, RAL_RF2, ral_rf2526_hi_r2[chan - 1]); + ral_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); + ral_rf_write(sc, RAL_RF1, 0x08804); + ral_rf_write(sc, RAL_RF2, ral_rf2526_r2[chan - 1]); + ral_rf_write(sc, RAL_RF3, power << 7 | 0x18044); + ral_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); + break; + /* dual-band RF */ case RAL_RF_5222: for (i = 0; i < N(ral_rf5222); i++) @@ -2382,18 +2426,17 @@ RAL_WRITE(sc, RAL_CSR13, 0); logcwmin = 5; - preload = (ic->ic_opmode == IEEE80211_M_IBSS) ? 1024 : 384; + preload = (ic->ic_opmode == IEEE80211_M_STA) ? 384 : 1024; tmp = logcwmin << 16 | preload; - RAL_WRITE(sc, RAL_BCNCSR1, tmp); + RAL_WRITE(sc, RAL_BCNOCSR, tmp); /* finally, enable TSF synchronization */ if (ic->ic_opmode == IEEE80211_M_STA) - RAL_WRITE(sc, RAL_CSR14, RAL_CSR14_TSF_SYNC_BSS | - RAL_CSR14_TSF_AUTOCOUNT | RAL_CSR14_BCN_RELOAD); + tmp |= RAL_ENABLE_TSF_SYNC(1); else - RAL_WRITE(sc, RAL_CSR14, RAL_CSR14_TSF_SYNC_IBSS | - RAL_CSR14_TSF_AUTOCOUNT | RAL_CSR14_BCN_RELOAD | - RAL_CSR14_GENERATE_BEACON); + tmp |= RAL_ENABLE_TSF_SYNC(2) | RAL_ENABLE_BEACON_GENERATOR; + + RAL_WRITE(sc, RAL_CSR14, tmp); DPRINTF(("enabling TSF synchronization\n")); } @@ -2404,18 +2447,18 @@ struct ieee80211com *ic = &sc->sc_ic; /* no short preamble for 1Mbps */ - RAL_WRITE(sc, RAL_ARCSR2, 0x00700400); + RAL_WRITE(sc, RAL_PLCP1MCSR, 0x00700400); if (!(ic->ic_flags & IEEE80211_F_SHPREAMBLE)) { /* values taken from the reference driver */ - RAL_WRITE(sc, RAL_ARCSR3, 0x00380401); - RAL_WRITE(sc, RAL_ARCSR4, 0x00150402); - RAL_WRITE(sc, RAL_ARCSR5, 0x000b8403); + RAL_WRITE(sc, RAL_PLCP2MCSR, 0x00380401); + RAL_WRITE(sc, RAL_PLCP5p5MCSR, 0x00150402); + RAL_WRITE(sc, RAL_PLCP11MCSR, 0x000b8403); } else { /* same values as above or'ed 0x8 */ - RAL_WRITE(sc, RAL_ARCSR3, 0x00380409); - RAL_WRITE(sc, RAL_ARCSR4, 0x0015040a); - RAL_WRITE(sc, RAL_ARCSR5, 0x000b840b); + RAL_WRITE(sc, RAL_PLCP2MCSR, 0x00380409); + RAL_WRITE(sc, RAL_PLCP5p5MCSR, 0x0015040a); + RAL_WRITE(sc, RAL_PLCP11MCSR, 0x000b840b); } DPRINTF(("updating PLCP for %s preamble\n", @@ -2518,9 +2561,9 @@ tmp = RAL_READ(sc, RAL_RXCSR0); - tmp &= ~RAL_RXCSR0_DROP_NOT_TO_ME; + tmp &= ~RAL_DROP_NOT_TO_ME; if (!(ifp->if_flags & IFF_PROMISC)) - tmp |= RAL_RXCSR0_DROP_NOT_TO_ME; + tmp |= RAL_DROP_NOT_TO_ME; RAL_WRITE(sc, RAL_RXCSR0, tmp); @@ -2528,6 +2571,54 @@ "entering" : "leaving")); } +static void +ral_set_txantenna(struct ral_softc *sc, int antenna) +{ + uint32_t tmp; + uint8_t tx; + + tx = ral_bbp_read(sc, RAL_BBP_TX) & ~RAL_BBP_ANTMASK; + if (antenna == 1) + tx |= RAL_BBP_ANTA; + else if (antenna == 2) + tx |= RAL_BBP_ANTB; + else + tx |= RAL_BBP_DIVERSITY; + + /* need to force I/Q flip for RF 2525e, 2526 and 5222 */ + if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526 || + sc->rf_rev == RAL_RF_5222) + tx |= RAL_BBP_FLIPIQ; + + ral_bbp_write(sc, RAL_BBP_TX, tx); + + /* update values for CCK and OFDM in BBPCSR1 */ + tmp = RAL_READ(sc, RAL_BBPCSR1) & ~0x00070007; + tmp |= (tx & 0x7) << 16 | (tx & 0x7); + RAL_WRITE(sc, RAL_BBPCSR1, tmp); +} + +static void +ral_set_rxantenna(struct ral_softc *sc, int antenna) +{ + uint8_t rx; + + rx = ral_bbp_read(sc, RAL_BBP_RX) & ~RAL_BBP_ANTMASK; + if (antenna == 1) + rx |= RAL_BBP_ANTA; + else if (antenna == 2) + rx |= RAL_BBP_ANTB; + else + rx |= RAL_BBP_DIVERSITY; + + /* need to force no I/Q flip for RF 2525e and 2526 */ + if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526) + rx &= ~RAL_BBP_FLIPIQ; + + ral_bbp_write(sc, RAL_BBP_RX, rx); +} + + static const char * ral_get_rf(int rev) { @@ -2537,6 +2628,7 @@ case RAL_RF_2524: return "RT2524"; case RAL_RF_2525: return "RT2525"; case RAL_RF_2525E: return "RT2525e"; + case RAL_RF_2526: return "RT2526"; case RAL_RF_5222: return "RT5222"; default: return "unknown"; } @@ -2548,7 +2640,7 @@ uint16_t val; int i; - val = ral_eeprom_read(sc, RAL_EEPROM_ANTENNA); + val = ral_eeprom_read(sc, RAL_EEPROM_CONFIG0); sc->rf_rev = (val >> 11) & 0x1f; sc->hw_radio = (val >> 10) & 0x1; sc->led_mode = (val >> 6) & 0x7; @@ -2565,7 +2657,7 @@ /* read Tx power for all b/g channels */ for (i = 0; i < 14 / 2; i++) { - val = ral_eeprom_read(sc, RAL_EEPROM_TXPOWER_BASE + i); + val = ral_eeprom_read(sc, RAL_EEPROM_TXPOWER + i); sc->txpow[i * 2] = val >> 8; sc->txpow[i * 2 + 1] = val & 0xff; } @@ -2627,10 +2719,11 @@ RAL_TX_RING_COUNT << 8 | RAL_TX_DESC_SIZE; + /* rings _must_ be initialized in this _exact_ order! */ RAL_WRITE(sc, RAL_TXCSR2, tmp); RAL_WRITE(sc, RAL_TXCSR3, sc->txq.physaddr); - RAL_WRITE(sc, RAL_TXCSR4, sc->atimq.physaddr); RAL_WRITE(sc, RAL_TXCSR5, sc->prioq.physaddr); + RAL_WRITE(sc, RAL_TXCSR4, sc->atimq.physaddr); RAL_WRITE(sc, RAL_TXCSR6, sc->bcnq.physaddr); /* setup rx ring */ @@ -2646,19 +2739,17 @@ IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); ral_set_macaddr(sc, ic->ic_myaddr); - /* set power mode (CAM) */ - RAL_WRITE(sc, RAL_TXCSR7, 0); - /* set supported basic rates (1, 2, 6, 12, 24) */ - RAL_WRITE(sc, RAL_ARCSR1, 0x153); + RAL_WRITE(sc, RAL_ARSP_PLCP_1, 0x153); + ral_set_txantenna(sc, 1); + ral_set_rxantenna(sc, 1); ral_update_slot(sc); ral_update_plcp(sc); ral_update_led(sc, 0, 0); - /* set soft reset and host ready */ - RAL_WRITE(sc, RAL_CSR1, RAL_CSR1_SOFT_RESET); - RAL_WRITE(sc, RAL_CSR1, RAL_CSR1_HOST_READY); + RAL_WRITE(sc, RAL_CSR1, RAL_RESET_ASIC); + RAL_WRITE(sc, RAL_CSR1, RAL_HOST_READY); if (ral_bbp_init(sc) != 0) { ral_stop(ifp, 1); @@ -2670,12 +2761,13 @@ ral_set_chan(sc, ic->ic_bss->ni_chan); /* kick Rx */ - tmp = RAL_RXCSR0_DROP_PHY | RAL_RXCSR0_DROP_CRC; + tmp = RAL_DROP_PHY_ERROR | RAL_DROP_CRC_ERROR; if (ic->ic_opmode != IEEE80211_M_MONITOR) { - tmp |= RAL_RXCSR0_DROP_CTL | RAL_RXCSR0_DROP_TODS | - RAL_RXCSR0_DROP_BAD_VERSION; + tmp |= RAL_DROP_CTL | RAL_DROP_VERSION_ERROR; + if (ic->ic_opmode != IEEE80211_M_HOSTAP) + tmp |= RAL_DROP_TODS; if (!(ifp->if_flags & IFF_PROMISC)) - tmp |= RAL_RXCSR0_DROP_NOT_TO_ME; + tmp |= RAL_DROP_NOT_TO_ME; } RAL_WRITE(sc, RAL_RXCSR0, tmp); @@ -2687,7 +2779,7 @@ RAL_WRITE(sc, RAL_CSR7, 0xffffffff); /* enable interrupts */ - RAL_WRITE(sc, RAL_CSR8, RAL_CSR8_MASK); + RAL_WRITE(sc, RAL_CSR8, RAL_INTR_MASK); ifp->if_flags &= ~IFF_OACTIVE; ifp->if_flags |= IFF_RUNNING; @@ -2710,13 +2802,13 @@ ieee80211_new_state(ic, IEEE80211_S_INIT, -1); /* abort Tx */ - RAL_WRITE(sc, RAL_TXCSR0, RAL_TXCSR0_ABORT); + RAL_WRITE(sc, RAL_TXCSR0, RAL_ABORT_TX); /* disable Rx */ - RAL_WRITE(sc, RAL_RXCSR0, RAL_RXCSR0_DISABLE); + RAL_WRITE(sc, RAL_RXCSR0, RAL_DISABLE_RX); /* reset ASIC (and thus, BBP) */ - RAL_WRITE(sc, RAL_CSR1, RAL_CSR1_SOFT_RESET); + RAL_WRITE(sc, RAL_CSR1, RAL_RESET_ASIC); RAL_WRITE(sc, RAL_CSR1, 0); /* disable interrupts */ @@ -2724,8 +2816,8 @@ /* reset Tx and Rx rings */ ral_reset_tx_ring(sc, &sc->txq); - ral_reset_tx_ring(sc, &sc->prioq); ral_reset_tx_ring(sc, &sc->atimq); + ral_reset_tx_ring(sc, &sc->prioq); ral_reset_tx_ring(sc, &sc->bcnq); ral_reset_rx_ring(sc, &sc->rxq); diff -ru ral-netbsd-1.0/src/sys/dev/ic/ralreg.h ral-current-netbsd-current/src/sys/dev/ic/ralreg.h --- ral-netbsd-1.0/src/sys/dev/ic/ralreg.h 2005-03-12 12:44:41.000000000 +0100 +++ ral-current-netbsd-current/src/sys/dev/ic/ralreg.h 2005-05-03 14:50:19.000000000 +0200 @@ -1,4 +1,4 @@ -/* $NetBSD$ */ +/* $OpenBSD: ralreg.h,v 1.5 2005/04/01 11:12:57 damien Exp $ */ /*- * Copyright (c) 2005 @@ -28,142 +28,148 @@ #define RAL_MAX_SCATTER 1 -#define RAL_CSR0 0x0000 -#define RAL_CSR1 0x0004 -#define RAL_CSR2 0x0008 -#define RAL_CSR3 0x000c -#define RAL_CSR4 0x0010 -#define RAL_CSR5 0x0014 -#define RAL_CSR6 0x0018 -#define RAL_CSR7 0x001c -#define RAL_CSR8 0x0020 -#define RAL_CSR9 0x0024 -#define RAL_CSR11 0x002c -#define RAL_CSR12 0x0030 -#define RAL_CSR13 0x0034 -#define RAL_CSR14 0x0038 -#define RAL_CSR15 0x003c -#define RAL_CSR16 0x0040 -#define RAL_CSR17 0x0044 -#define RAL_CSR18 0x0048 -#define RAL_CSR19 0x004c -#define RAL_CSR20 0x0050 -#define RAL_CSR21 0x0054 -#define RAL_CSR22 0x0058 - -#define RAL_SECCSR0 0x0028 -#define RAL_SECCSR1 0x0158 -#define RAL_SECCSR3 0x00fc - -#define RAL_TXCSR0 0x0060 -#define RAL_TXCSR1 0x0064 -#define RAL_TXCSR2 0x0068 -#define RAL_TXCSR3 0x006c -#define RAL_TXCSR4 0x0070 -#define RAL_TXCSR5 0x0074 -#define RAL_TXCSR6 0x0078 -#define RAL_TXCSR7 0x007c -#define RAL_TXCSR8 0x0098 -#define RAL_TXCSR9 0x0094 - -#define RAL_RXCSR0 0x0080 -#define RAL_RXCSR1 0x0084 -#define RAL_RXCSR2 0x0088 -#define RAL_RXCSR3 0x0090 -#define RAL_ARCSR1 0x009c - -#define RAL_PCICSR 0x008c - -#define RAL_CNT0 0x00a0 -#define RAL_CNT1 0x00ac -#define RAL_CNT2 0x00b0 -#define RAL_CNT3 0x00b8 -#define RAL_CNT4 0x00bc -#define RAL_CNT5 0x00c0 - -#define RAL_PWRCSR0 0x00c4 -#define RAL_PSCSR0 0x00c8 -#define RAL_PSCSR1 0x00cc -#define RAL_PSCSR2 0x00d0 -#define RAL_PSCSR3 0x00d4 -#define RAL_PWRCSR1 0x00d8 -#define RAL_TIMECSR 0x00dc -#define RAL_MACCSR0 0x00e0 -#define RAL_MACCSR1 0x00e4 -#define RAL_RALINKCSR 0x00e8 -#define RAL_BCNCSR 0x00ec - -#define RAL_BBPCSR 0x00f0 -#define RAL_RFCSR 0x00f4 -#define RAL_LEDCSR 0x00f8 - -#define RAL_TXACKCSR0 0x0110 -#define RAL_ACKCNT0 0x0114 -#define RAL_ACKCNT1 0x0118 - -#define RAL_GPIOCSR 0x0120 -#define RAL_FIFOCSR0 0x0128 -#define RAL_FIFOCSR1 0x012C -#define RAL_BCNCSR1 0x0130 -#define RAL_MACCSR2 0x0134 -#define RAL_TESTCSR 0x0138 - -#define RAL_ARCSR2 0x013c -#define RAL_ARCSR3 0x0140 -#define RAL_ARCSR4 0x0144 -#define RAL_ARCSR5 0x0148 - -#define RAL_ARTCSR0 0x014c -#define RAL_ARTCSR1 0x0150 -#define RAL_ARTCSR2 0x0154 -#define RAL_SECCSR1 0x0158 -#define RAL_BBPCSR1 0x015c - - -#define RAL_CSR1_SOFT_RESET (1 << 0) -#define RAL_CSR1_HOST_READY (1 << 2) - -#define RAL_CSR21_93C46 (1 << 5) - -#define RAL_TXCSR0_KICK_TX (1 << 0) -#define RAL_TXCSR0_KICK_ATIM (1 << 1) -#define RAL_TXCSR0_KICK_PRIO (1 << 2) -#define RAL_TXCSR0_ABORT (1 << 3) - -#define RAL_RXCSR0_DISABLE (1 << 0) -#define RAL_RXCSR0_DROP_CRC (1 << 1) -#define RAL_RXCSR0_DROP_PHY (1 << 2) -#define RAL_RXCSR0_DROP_CTL (1 << 3) -#define RAL_RXCSR0_DROP_NOT_TO_ME (1 << 4) -#define RAL_RXCSR0_DROP_TODS (1 << 5) -#define RAL_RXCSR0_DROP_BAD_VERSION (1 << 6) +/* + * Control and status registers. + */ +#define RAL_CSR0 0x0000 /* ASIC version number */ +#define RAL_CSR1 0x0004 /* System control */ +#define RAL_CSR3 0x000c /* STA MAC address 0 */ +#define RAL_CSR4 0x0010 /* STA MAC address 1 */ +#define RAL_CSR5 0x0014 /* BSSID 0 */ +#define RAL_CSR6 0x0018 /* BSSID 1 */ +#define RAL_CSR7 0x001c /* Interrupt source */ +#define RAL_CSR8 0x0020 /* Interrupt mask */ +#define RAL_CSR9 0x0024 /* Maximum frame length */ +#define RAL_SECCSR0 0x0028 /* WEP control */ +#define RAL_CSR11 0x002c /* Back-off control */ +#define RAL_CSR12 0x0030 /* Synchronization configuration 0 */ +#define RAL_CSR13 0x0034 /* Synchronization configuration 1 */ +#define RAL_CSR14 0x0038 /* Synchronization control */ +#define RAL_CSR15 0x003c /* Synchronization status */ +#define RAL_CSR16 0x0040 /* TSF timer 0 */ +#define RAL_CSR17 0x0044 /* TSF timer 1 */ +#define RAL_CSR18 0x0048 /* IFS timer 0 */ +#define RAL_CSR19 0x004c /* IFS timer 1 */ +#define RAL_CSR20 0x0050 /* WAKEUP timer */ +#define RAL_CSR21 0x0054 /* EEPROM control */ +#define RAL_CSR22 0x0058 /* CFP control */ +#define RAL_TXCSR0 0x0060 /* TX control */ +#define RAL_TXCSR1 0x0064 /* TX configuration */ +#define RAL_TXCSR2 0x0068 /* TX descriptor configuration */ +#define RAL_TXCSR3 0x006c /* TX ring base address */ +#define RAL_TXCSR4 0x0070 /* TX ATIM ring base address */ +#define RAL_TXCSR5 0x0074 /* TX PRIO ring base address */ +#define RAL_TXCSR6 0x0078 /* Beacon base address */ +#define RAL_TXCSR7 0x007c /* AutoResponder control */ +#define RAL_RXCSR0 0x0080 /* RX control */ +#define RAL_RXCSR1 0x0084 /* RX descriptor configuration */ +#define RAL_RXCSR2 0x0088 /* RX ring base address */ +#define RAL_PCICSR 0x008c /* PCI control */ +#define RAL_RXCSR3 0x0090 /* BBP ID 0 */ +#define RAL_TXCSR9 0x0094 /* OFDM TX BBP */ +#define RAL_ARSP_PLCP_0 0x0098 /* Auto Responder PLCP address */ +#define RAL_ARSP_PLCP_1 0x009c /* Auto Responder PLCP Basic Rate bit mask */ +#define RAL_CNT0 0x00a0 /* FCS error counter */ +#define RAL_CNT1 0x00ac /* PLCP error counter */ +#define RAL_CNT2 0x00b0 /* Long error counter */ +#define RAL_CNT3 0x00b8 /* CCA false alarm counter */ +#define RAL_CNT4 0x00bc /* RX FIFO Overflow counter */ +#define RAL_CNT5 0x00c0 /* Tx FIFO Underrun counter */ +#define RAL_PWRCSR0 0x00c4 /* Power mode configuration */ +#define RAL_PSCSR0 0x00c8 /* Power state transition time */ +#define RAL_PSCSR1 0x00cc /* Power state transition time */ +#define RAL_PSCSR2 0x00d0 /* Power state transition time */ +#define RAL_PSCSR3 0x00d4 /* Power state transition time */ +#define RAL_PWRCSR1 0x00d8 /* Manual power control/status */ +#define RAL_TIMECSR 0x00dc /* Timer control */ +#define RAL_MACCSR0 0x00e0 /* MAC configuration */ +#define RAL_MACCSR1 0x00e4 /* MAC configuration */ +#define RAL_RALINKCSR 0x00e8 /* Ralink RX auto-reset BBCR */ +#define RAL_BCNCSR 0x00ec /* Beacon interval control */ +#define RAL_BBPCSR 0x00f0 /* BBP serial control */ +#define RAL_RFCSR 0x00f4 /* RF serial control */ +#define RAL_LEDCSR 0x00f8 /* LED control */ +#define RAL_SECCSR3 0x00fc /* XXX not documented */ +#define RAL_DMACSR0 0x0100 /* Current RX ring address */ +#define RAL_DMACSR1 0x0104 /* Current Tx ring address */ +#define RAL_DMACSR2 0x0104 /* Current Priority ring address */ +#define RAL_DMACSR3 0x0104 /* Current ATIM ring address */ +#define RAL_TXACKCSR0 0x0110 /* XXX not documented */ +#define RAL_GPIOCSR 0x0120 /* */ +#define RAL_BBBPPCSR 0x0124 /* BBP Pin Control */ +#define RAL_FIFOCSR0 0x0128 /* TX FIFO pointer */ +#define RAL_FIFOCSR1 0x012c /* RX FIFO pointer */ +#define RAL_BCNOCSR 0x0130 /* Beacon time offset */ +#define RAL_RLPWCSR 0x0134 /* RX_PE Low Width */ +#define RAL_TESTCSR 0x0138 /* Test Mode Select */ +#define RAL_PLCP1MCSR 0x013c /* Signal/Service/Length of ACK/CTS @1M */ +#define RAL_PLCP2MCSR 0x0140 /* Signal/Service/Length of ACK/CTS @2M */ +#define RAL_PLCP5p5MCSR 0x0144 /* Signal/Service/Length of ACK/CTS @5.5M */ +#define RAL_PLCP11MCSR 0x0148 /* Signal/Service/Length of ACK/CTS @11M */ +#define RAL_ACKPCTCSR 0x014c /* ACK/CTS padload consume time */ +#define RAL_ARTCSR1 0x0150 /* ACK/CTS padload consume time */ +#define RAL_ARTCSR2 0x0154 /* ACK/CTS padload consume time */ +#define RAL_SECCSR1 0x0158 /* WEP control */ +#define RAL_BBPCSR1 0x015c /* BBP TX Configuration */ + + +/* possible flags for register RXCSR0 */ +#define RAL_DISABLE_RX (1 << 0) +#define RAL_DROP_CRC_ERROR (1 << 1) +#define RAL_DROP_PHY_ERROR (1 << 2) +#define RAL_DROP_CTL (1 << 3) +#define RAL_DROP_NOT_TO_ME (1 << 4) +#define RAL_DROP_TODS (1 << 5) +#define RAL_DROP_VERSION_ERROR (1 << 6) + +/* possible flags for register CSR1 */ +#define RAL_RESET_ASIC (1 << 0) +#define RAL_RESET_BBP (1 << 1) +#define RAL_HOST_READY (1 << 2) + +/* possible flags for register CSR14 */ +#define RAL_ENABLE_TSF (1 << 0) +#define RAL_ENABLE_TSF_SYNC(x) (((x) & 0x3) << 1) +#define RAL_ENABLE_TBCN (1 << 3) +#define RAL_ENABLE_BEACON_GENERATOR (1 << 6) + +/* possible flags for register CSR21 */ +#define RAL_EEPROM_C (1 << 1) +#define RAL_EEPROM_S (1 << 2) +#define RAL_EEPROM_D (1 << 3) +#define RAL_EEPROM_Q (1 << 4) +#define RAL_EEPROM_93C46 (1 << 5) -#define RAL_SECCSR0_KICK (1 << 0) +#define RAL_EEPROM_SHIFT_D 3 +#define RAL_EEPROM_SHIFT_Q 4 -#define RAL_SECCSR1_KICK (1 << 0) +/* possible flags for register TXCSR0 */ +#define RAL_KICK_TX (1 << 0) +#define RAL_KICK_ATIM (1 << 1) +#define RAL_KICK_PRIO (1 << 2) +#define RAL_ABORT_TX (1 << 3) + +/* possible flags for register SECCSR0 */ +#define RAL_KICK_DECRYPT (1 << 0) + +/* possible flags for register SECCSR1 */ +#define RAL_KICK_ENCRYPT (1 << 0) /* possible flags for register CSR7 */ -#define RAL_CSR7_BEACON_EXPIRE 0x00000001 -#define RAL_CSR7_WAKEUP_EXPIRE 0x00000002 -#define RAL_CSR7_ATIM_EXPIRE 0x00000004 -#define RAL_CSR7_TX_DONE 0x00000008 -#define RAL_CSR7_ATIM_DONE 0x00000010 -#define RAL_CSR7_PRIO_DONE 0x00000020 -#define RAL_CSR7_RX_DONE 0x00000040 -#define RAL_CSR7_DECRYPTION_DONE 0x00000080 -#define RAL_CSR7_ENCRYPTION_DONE 0x00000100 - -#define RAL_CSR8_MASK \ - (~(RAL_CSR7_BEACON_EXPIRE | RAL_CSR7_WAKEUP_EXPIRE | \ - RAL_CSR7_TX_DONE | RAL_CSR7_PRIO_DONE | RAL_CSR7_RX_DONE | \ - RAL_CSR7_DECRYPTION_DONE | RAL_CSR7_ENCRYPTION_DONE)) - -#define RAL_CSR14_TSF_AUTOCOUNT (1 << 0) -#define RAL_CSR14_TSF_SYNC_BSS (1 << 1) -#define RAL_CSR14_TSF_SYNC_IBSS (2 << 1) -#define RAL_CSR14_BCN_RELOAD (1 << 3) -#define RAL_CSR14_GENERATE_BEACON (1 << 6) -#define RAL_CSR14_PRELOAD_SHIFT 16 +#define RAL_BEACON_EXPIRE 0x00000001 +#define RAL_WAKEUP_EXPIRE 0x00000002 +#define RAL_ATIM_EXPIRE 0x00000004 +#define RAL_TX_DONE 0x00000008 +#define RAL_ATIM_DONE 0x00000010 +#define RAL_PRIO_DONE 0x00000020 +#define RAL_RX_DONE 0x00000040 +#define RAL_DECRYPTION_DONE 0x00000080 +#define RAL_ENCRYPTION_DONE 0x00000100 + +#define RAL_INTR_MASK \ + (~(RAL_BEACON_EXPIRE | RAL_WAKEUP_EXPIRE | RAL_TX_DONE | \ + RAL_PRIO_DONE | RAL_RX_DONE | RAL_DECRYPTION_DONE | \ + RAL_ENCRYPTION_DONE)) /* Tx descriptor */ struct ral_tx_desc { @@ -178,16 +184,16 @@ #define RAL_TX_FAIL_INVALID (3 << 2) #define RAL_TX_FAIL_OTHER (4 << 2) -#define RAL_TX_NOT_LAST (1 << 8) -#define RAL_TX_NEED_ACK (1 << 9) -#define RAL_TX_INSERT_TIMESTAMP (1 << 10) +#define RAL_TX_MORE_FRAG (1 << 8) +#define RAL_TX_ACK (1 << 9) +#define RAL_TX_TIMESTAMP (1 << 10) #define RAL_TX_OFDM (1 << 11) #define RAL_TX_CIPHER_BUSY (1 << 12) #define RAL_TX_IFS_MASK 0x00006000 #define RAL_TX_IFS_BACKOFF (0 << 13) #define RAL_TX_IFS_SIFS (1 << 13) -#define RAL_TX_IFS_NEW_BACKOFF (2 << 13) +#define RAL_TX_IFS_NEWBACKOFF (2 << 13) #define RAL_TX_IFS_NONE (3 << 13) #define RAL_TX_LONG_RETRY (1 << 15) @@ -200,11 +206,13 @@ #define RAL_TX_CIPHER_AES (4 << 29) uint32_t physaddr; - uint32_t wme; -#define RAL_WME_CWMAX_BITS_SHIFT 12 -#define RAL_WME_CWMIN_BITS_SHIFT 8 -#define RAL_WME_AIFSN_BITS_SHIFT 6 + uint16_t wme; +#define RAL_LOGCWMAX(x) (((x) & 0xf) << 12) +#define RAL_LOGCWMIN(x) (((x) & 0xf) << 8) +#define RAL_AIFSN(x) (((x) & 0x3) << 6) +#define RAL_IVOFFSET(x) (((x) & 0x3f)) + uint16_t reserved1; uint8_t plcp_signal; uint8_t plcp_service; #define RAL_PLCP_LENGEXT 0x80 @@ -213,7 +221,7 @@ uint32_t iv; uint32_t eiv; uint8_t key[IEEE80211_KEYBUF_SIZE]; - uint32_t reserved[2]; + uint32_t reserved2[2]; } __packed; /* Rx descriptor */ @@ -252,18 +260,27 @@ #define RAL_BBP_BUSY (1 << 15) #define RAL_BBP_WRITE (1 << 16) -#define RAL_RF_BUSY (1 << 31) #define RAL_RF_20BIT (20 << 24) +#define RAL_RF_BUSY (1 << 31) #define RAL_RF_2522 0x00 #define RAL_RF_2523 0x01 #define RAL_RF_2524 0x02 #define RAL_RF_2525 0x03 #define RAL_RF_2525E 0x04 +#define RAL_RF_2526 0x05 /* dual-band RF */ #define RAL_RF_5222 0x10 #define RAL_BBP_VERSION 0 +#define RAL_BBP_TX 2 +#define RAL_BBP_RX 14 + +#define RAL_BBP_ANTA 0x00 +#define RAL_BBP_DIVERSITY 0x01 +#define RAL_BBP_ANTB 0x02 +#define RAL_BBP_ANTMASK 0x03 +#define RAL_BBP_FLIPIQ 0x04 #define RAL_LED_MODE_DEFAULT 0 #define RAL_LED_MODE_TXRX_ACTIVITY 1 @@ -272,25 +289,12 @@ #define RAL_JAPAN_FILTER 0x8 -#define RAL_EEPROM_ANTENNA 16 -#define RAL_EEPROM_CONFIG 17 -#define RAL_EEPROM_COUNTRY 18 +#define RAL_EEPROM_CONFIG0 16 #define RAL_EEPROM_BBP_BASE 19 -#define RAL_EEPROM_TXPOWER_BASE 35 -#define RAL_EEPROM_TSSI_BASE 42 -#define RAL_EEPROM_RSSITODBM 62 -#define RAL_EEPROM_VERSION 63 +#define RAL_EEPROM_TXPOWER 35 #define RAL_EEPROM_DELAY 1 /* minimum hold time (microsecond) */ -#define RAL_EEPROM_C (1 << 1) /* Serial Clock */ -#define RAL_EEPROM_S (1 << 2) /* Chip Select */ -#define RAL_EEPROM_D (1 << 3) /* Serial data input */ -#define RAL_EEPROM_Q (1 << 4) /* Serial data output */ - -#define RAL_EEPROM_SHIFT_D 3 -#define RAL_EEPROM_SHIFT_Q 4 - /* * control and status registers access macros */